1. Technical Field
The present invention relates to a semiconductor memory apparatus and, more particularly, to a memory cell of a semiconductor memory apparatus and a control circuit thereof.
2. Related Art
A conventional dynamic random access memory (DRAM) includes numerous memory cells that are each composed of one transistor and one capacitor to store data. However, a general structure having those memory cells is not suitable to decrease an area of a memory core region, such that there is a technical limitation in improving an integration degree of a semiconductor memory apparatus. Therefore, a floating body cell (FBC) technology for implementing the transistor and the capacitor of the memory cell as one transistor has been developed.
Hereinafter, the FBC technology will be described in more detail with reference to the accompanying drawings.
FIG. 1 is a cross-sectional view of a transistor implementing an FBC and illustrates an N-type transistor as an example. It is understood herein that the drawings are not necessarily to scale and in some instances proportions may have been exaggerated in order to more clearly depict certain features of the invention.
As shown in FIG. 1, like a general N-type MOS transistor, the transistor implementing the FBC has a structure in which a source 1 and a drain 2 doped with N-type impurities are configured on a semiconductor substrate and a gate electrode 3 and a gate oxide layer 4 are formed at a predetermined region of a top part of the source 1 and the drain 2. However, an insulating layer 5 is provided in a center portion of a body region. Therefore, the body region is divided into a floating body part 6 and a substrate part 7. At this time, the floating body part 6 and the substrate part 7 are doped with P-type impurities.
The insulating layer 5 is interposed between the floating body part 6 and the substrate part 7, such that holes are accumulated in the floating body part 6 by voltages respectively applied to the source 1, the drain 2, and the gate electrode 3. Therefore, a virtual capacitor is formed in the FBC. Due to characteristics of the capacitor generated as above, the transistor can be utilized as a memory cell having a structure in which a switching transistor and the memory cell are combined with each other.
In order to implement the FBC technology, a predetermined voltage must be accurately applied to each of the source, the drain, and the gate of the transistor in a read operation or a write operation. Further, in the FBC technology, a support for a hold operation is required as well as the read and write operations and an operation of inputting a logical value of ‘1’, and an operation of inputting a logical value of ‘0’ need to be distinguished even during the write operation.
Likewise, levels of voltages to be applied to the source, the drain, and the gate are shown in Table 1 depending on each operation.
TABLE 1Write ‘1’Write ‘0’ReadHoldoperationoperationoperationoperationSource2.5 V2.5 V2.5 V0 VvoltageDrain  0 V0.5 V  0 V0 VvoltageGate voltage0.5 V0.5 V−1.0 V −1.5 V  
As seen from Table 1, a cell transistor in the FBC technology should be applied with voltages set at a source, a drain, and a gate thereof at the time of performing four different operations. For this, a circuit for supplying a voltage to each of the source, the drain, and the gate of the cell transistor for each operation should be provided.
Up to now, the FBC technology is difficult to utilize as the memory cell of the semiconductor memory apparatus because circuits for supplying voltages to the source, the drain, and the gate of each cell transistor have not yet been developed. Moreover, data of the semiconductor memory apparatus adopting the FBC technology are also volatile like in the DRAM. Therefore, even herein, a refresh operation should be performed and the relevant technical configuration should be provided. As such, development of relevant circuits is keenly necessary in order to adopt the FBC technology for improving the integration degree of the semiconductor memory apparatus.